Silicon-based integrated circuits have long been the mainstay of the electronics industry, driving products to become smaller and faster based on the predictions made by Moore's Law. Recently however, these scaling trends have slowed due to difficulties in fabricating nanometer scale devices. It is predicted that soon, lithographic based fabrication will reach a barrier when attempting to pattern devices containing only a few atoms per transistor. Research efforts are in place to find a solution to these lithographic limitations within the standard CMOS process.
Many novel technologies have been proposed as alternatives to the traditional CMOS process. A few of such devices are carbon nanotubes, quantum cellular automata (QCA), single electron transistors, and molecular devices. Carbon nanotubes are popular devices among researchers due to their potential for extremely fast operating speeds. The problem with carbon nanotubes lies in the difficulty to accurately place large quantities of nanotubes in a patterned layout. QCA presents a simple concept to creating nano-electronic logic; however, QCA suffers from the lack of any fault tolerance within the architecture itself. Single electron transistors also are popular due to their potential for extremely high switching speeds; however single electron transistors suffer from the inability to operate anywhere near room temperature. Single electron transistors generally require temperatures below 20° Kelvin for stability. Molecular devices allow for fast switching speeds, while being able to operate at room temperature. Since the standard architecture for these devices is the regular crossbar array, it is easy to pattern and layout large quantities of these devices useful for both memory and logic.
Additional benefits of molecular devices pertain specifically to non-volatile memory design. Certain molecules, such as Rotaxane and nitro-based OPE (Oligophenylene ethynylenes), have two different conductivity states when placed into a crossbar array based design. One state is a high conductivity state, and the other is a low conductivity state. These two states represent the equivalents of logic ‘1’ and logic ‘0’ as found in memories such as SRAM and DRAM. Using these devices in the crossbar array yields a molecular-based, non-volatile memory architecture. This particular memory architecture is of interest mainly due to the device density. The ITRS (International Technology Roadmap for Semiconductors) states that molecular memories have the smallest demonstrated and projected cell area of 30 nm and 5 nm respectively, and the smallest projected feature size of 5F2.
One large drawback of this molecular memory architecture is that as the memory size grows larger, introducing more devices into the crossbar array, the more difficult it becomes to distinguish a logic ‘1’ from a logic ‘0’. This is due to the parasitic current paths existing within the crossbar array itself. In fact, this is an intrinsic problem with the crossbar array and exists in any memory array based on this crossbar architecture. One potential solution to this problem is to make the devices themselves act more like true diodes. In this sense, current could not flow through the parasitic paths of the crossbar array because certain devices would be reverse-biased, allowing only minutely small amounts of current to leak through the array. However, in practice this would be difficult to achieve, merely due to the scale of the devices within the architecture. Most of these molecules are only a few angstroms long, which will elicit band-to-band tunneling across the device even if the molecule is indeed more diode-like.
Thus, there exists a need to eliminate the effects of these parasitic current paths, allowing for larger, readable crossbar-array based memory arrays to be obtained.